Issued Patents 2022
Showing 1–17 of 17 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11507528 | Pooled memory address translation | — | 2022-11-22 |
| 11474960 | Technologies for partial link width states for multilane links | — | 2022-10-18 |
| 11467999 | Negotiating asymmetric link widths dynamically in a multi-lane link | — | 2022-10-11 |
| 11444829 | Link layer communication by multiple link layer encodings for computer buses | — | 2022-09-13 |
| 11429553 | Flit-based packetization | — | 2022-08-30 |
| 11397701 | Retimer mechanisms for in-band link management | — | 2022-07-26 |
| 11386033 | Extending multichip package link off package | Zuoguo Wu, Mahesh Wagh, Mohiuddin M. Mazumder, Venkatraman Iyer, Jeff C. Morriss | 2022-07-12 |
| 11327861 | Cross-talk generation in a multi-lane link during lane testing | Daniel S. Froelich | 2022-05-10 |
| 11327920 | Recalibration of PHY circuitry for the PCI express (pipe) interface based on using a message bus interface | Michelle C. Jen, Minxi Gao, Fulvio Spagna, Bruce A. Tennant, Noam Dolev Geldbard | 2022-05-10 |
| 11296994 | Ordered sets for high-speed interconnects | — | 2022-04-05 |
| 11283466 | PCI express enhancements | Zuoguo Wu, Md. Mohiuddin Mazumder, Subas Bastola, Kai Xiao | 2022-03-22 |
| 11269793 | High performance interconnect | Robert J. Safranek, Robert G. Blankenship, Venkatraman Iyer, Jeff Willey, Robert Beers +18 more | 2022-03-08 |
| 11249837 | Flit-based parallel-forward error correction and parity | — | 2022-02-15 |
| 11249808 | Connecting accelerator resources using a switch | Anil Rao | 2022-02-15 |
| 11239843 | Width and frequency conversion with PHY layer devices in PCI-express | — | 2022-02-01 |
| 11232058 | Enabling sync header suppression latency optimization in the presence of retimers for serial interconnect | Michelle C. Jen, Bruce A. Tennant, Prahladachar Jayaprakash Bharadwaj | 2022-01-25 |
| 11223446 | Forward error correction mechanism for data transmission across multi-lane links | — | 2022-01-11 |