| 11537403 |
Control flow mechanism for execution of graphics processor instructions using active channel packing |
Subramaniam Maiyuran, Guei-Yuan Lueh, Gang Chen, Ananda V. Kommaraju, Joy Chandra +10 more |
2022-12-27 |
| 11507375 |
Hierarchical general register file (GRF) for execution block |
Abhishek R. Appu, Altug Koker, Joydeep Ray, Kamal Sinha, Kiran C. Veernapu +7 more |
2022-11-22 |
| 11443407 |
Sparse matrix optimization mechanism |
Namita Sharma, Biju P. Simon, Tovinakere D. Vivek |
2022-09-13 |
| 11361496 |
Graphics processors and graphics processing units having dot product accumulate instruction for hybrid floating point format |
Subramaniam Maiyuran, Shubra Marwaha, Ashutosh Garg, Jorge Parra, Chandra Gurram +3 more |
2022-06-14 |
| 11321799 |
Compiler assisted register file write reduction |
Chandra Gurram, Gang Chen, Subramaniam Maiyuran, Ashutosh Garg, Jorge Parra +3 more |
2022-05-03 |
| 11314515 |
Instructions and logic for vector multiply add with zero skipping |
Sasikanth Avancha, Ishwar Bhati, Wei-Yu Chen, Dipankar Das, Ashutosh Garg +7 more |
2022-04-26 |