Issued Patents 2022
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11537403 | Control flow mechanism for execution of graphics processor instructions using active channel packing | Subramaniam Maiyuran, Supratim Pal, Gang Chen, Ananda V. Kommaraju, Joy Chandra +10 more | 2022-12-27 |
| 11508338 | Register spill/fill using shared local memory space | Joydeep Ray, Altug Koker, Balaji Vembu, Murali Ramadoss, James Valerio +7 more | 2022-11-22 |
| 11507375 | Hierarchical general register file (GRF) for execution block | Abhishek R. Appu, Altug Koker, Joydeep Ray, Kamal Sinha, Kiran C. Veernapu +7 more | 2022-11-22 |
| 11361496 | Graphics processors and graphics processing units having dot product accumulate instruction for hybrid floating point format | Subramaniam Maiyuran, Shubra Marwaha, Ashutosh Garg, Supratim Pal, Jorge Parra +3 more | 2022-06-14 |
| 11354769 | Page faulting and selective preemption | Altug Koker, Ingo Wald, David Puffer, Subramaniam Maiyuran, Prasoonkumar Surti +4 more | 2022-06-07 |
| 11354768 | Intelligent graphics dispatching mechanism | Balaji Vembu, Murali Ramadoss, Subramaniam Maiyuran, Abhishek R. Appu, Joydeep Ray +4 more | 2022-06-07 |
| 11321799 | Compiler assisted register file write reduction | Chandra Gurram, Gang Chen, Subramaniam Maiyuran, Supratim Pal, Ashutosh Garg +3 more | 2022-05-03 |
| 11314515 | Instructions and logic for vector multiply add with zero skipping | Supratim Pal, Sasikanth Avancha, Ishwar Bhati, Wei-Yu Chen, Dipankar Das +7 more | 2022-04-26 |
| 11294670 | Method and apparatus for performing reduction operations on a plurality of associated data element values | Christopher J. Hughes, Jonathan Pearce, Elmoustapha Ould-Ahmed-Vall, Jorge Parra, Prasoonkumar Surti +2 more | 2022-04-05 |
| 11232536 | Thread prefetch mechanism | Adam T. Lake, Balaji Vembu, Murali Ramadoss, Prasoonkumar Surti, Abhishek R. Appu +8 more | 2022-01-25 |