Issued Patents 2022
Showing 1–22 of 22 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11527432 | Bulk substrates with a self-aligned buried polycrystalline layer | Steven M. Shank, Ian McCallum-Cook, Siva P. Adusumilli | 2022-12-13 |
| 11515397 | III-V compound semiconductor layer stacks with electrical isolation provided by a trap-rich layer | Siva P. Adusumilli, Vibhor Jain, Steven Bentley | 2022-11-29 |
| 11488980 | Wafer with localized semiconductor on insulator regions with cavity structures | Siva P. Adusumilli, Bruce W. Porth, John J. Ellis-Monaghan | 2022-11-01 |
| 11488950 | Integrated circuit structure and method for bipolar transistor stack within substrate | Uzma Rana, Vibhor Jain, Qizhi Liu, Siva P. Adusumilli | 2022-11-01 |
| 11469178 | Metal-free fuse structures | John J. Ellis-Monaghan, Steven M. Shank, John J. Pekarik, Vibhor Jain | 2022-10-11 |
| 11437522 | Field-effect transistors with a polycrystalline body in a shallow trench isolation region | Michel J. Abou-Khalil, Steven M. Shank, Mark D. Levy, Rajendran Krishnasamy, John J. Ellis-Monaghan | 2022-09-06 |
| 11411081 | Field effect transistor (FET) stack and methods to form same | Steven M. Shank, Vibhor Jain, John J. Ellis-Monaghan | 2022-08-09 |
| 11410872 | Oxidized cavity structures within and under semiconductor devices | Siva P. Adusumilli, Steven M. Shank, John J. Ellis-Monaghan | 2022-08-09 |
| 11380759 | Transistor with embedded isolation layer in bulk substrate | Uzma Rana, Johnatan A. Kantarovsky, Steven M. Shank, Siva P. Adusumilli | 2022-07-05 |
| 11380615 | Tight pitch wirings and capacitor(s) | Daisy A. Vaughn, Stephen R. Bosley, Zhong-Xiang He | 2022-07-05 |
| 11355409 | Chip package with emitter finger cells spaced by different spacings from a heat sink to provide reduced temperature variation | Hanyi Ding, Vibhor Jain, Alvin J. Joseph | 2022-06-07 |
| 11333558 | Boolean temperature sensing using phase transition material | Vibhor Jain, John J. Pekarik, Steven M. Shank | 2022-05-17 |
| 11322387 | Bulk wafer switch isolation | Uzma Rana, Steven M. Shank, Brett T. Cucci | 2022-05-03 |
| 11322357 | Buried damage layers for electrical isolation | Siva P. Adusumilli, Michel J. Abou-Khalil, John J. Ellis-Monaghan, Bojidha Babu | 2022-05-03 |
| 11316045 | Vertical field effect transistor (FET) with source and drain structures | Aaron L. Vallett, Steven M. Shank, John J. Ellis-Monaghan | 2022-04-26 |
| 11315825 | Semiconductor structures including stacked depleted and high resistivity regions | Michel J. Abou-Khalil, Aaron L. Vallett, Steven M. Shank, Bojidha Babu, John J. Ellis-Monaghan | 2022-04-26 |
| 11296190 | Field effect transistors with back gate contact and buried high resistivity layer | Vibhor Jain, Steven M. Shank, John J. Ellis-Monaghan, John J. Pekarik | 2022-04-05 |
| 11282883 | Trench-based photodiodes | John J. Ellis-Monaghan, Steven M. Shank, Vibhor Jain, John J. Pekarik | 2022-03-22 |
| 11271079 | Wafer with crystalline silicon and trap rich polysilicon layer | Steven M. Shank, John J. Pekarik, Vibhor Jain, John J. Ellis-Monaghan | 2022-03-08 |
| 11271077 | Trap-rich layer in a high-resistivity semiconductor layer | Vibhor Jain, John J. Pekarik, Steven M. Shank, John J. Ellis-Monaghan | 2022-03-08 |
| 11264499 | Transistor devices with source/drain regions comprising an interface layer that comprises a non-semiconductor material | John J. Pekarik, Steven M. Shank, Vibhor Jain, John J. Ellis-Monaghan | 2022-03-01 |
| 11264457 | Isolation trenches augmented with a trap-rich layer | Mark D. Levy, Siva P. Adusumilli, Steven M. Shank, Alvin J. Joseph | 2022-03-01 |