| 11500778 |
Prefetch kernels on data-parallel processors |
Nuwan Jayasena, James M. O'Connor |
2022-11-15 |
| 11494192 |
Pipeline including separate hardware data paths for different instruction types |
Jiasheng Chen, Yunxiao Zou, Bin He, Angel E. Socarras, QingCheng Wang +1 more |
2022-11-08 |
| 11467870 |
VMID as a GPU task container for virtualization |
Anirudh R. Acharya, Rex Eldon McCrary, Anthony Asaro, Jeffrey G. Cheng, Mark Fowler |
2022-10-11 |
| 11409536 |
Pairing SIMD lanes to perform double precision operations |
Bin He, Yunxiao Zou, Jiasheng Chen |
2022-08-09 |
| 11409840 |
Dynamically adaptable arrays for vector and matrix operations |
Sateesh Lagudu, Allen H. Rush, Arun Vaidyanathan Ananthanarayan, Prasad Nagabhushanamgari |
2022-08-09 |
| 11397578 |
Selectively dispatching waves based on accumulators holding behavioral characteristics of waves currently executing |
Randy Wayne Ramsey, William D. Isenberg |
2022-07-26 |
| 11386520 |
Redundancy method and apparatus for shader column repair |
Jeffrey T. Brady, Angel E. Socarras |
2022-07-12 |
| 11386518 |
Exception handler for sampling draw dispatch identifiers |
Alexander Fuad Ashkar, Randy Wayne Ramsey, Mangesh P. Nijasure, Brian D. Emberling |
2022-07-12 |
| 11379941 |
Primitive shader |
Todd Martin, Mangesh P. Nijasure, Randy Wayne Ramsey, Laurent Lefebvre |
2022-07-05 |
| 11335052 |
Hybrid render with deferred primitive batch binning |
Laurent Lefebvre, Mark Fowler, Timothy Kelley, Mikko Alho, Mika Tuomi +4 more |
2022-05-17 |
| 11295507 |
Spatial partitioning in a multi-tenancy graphics processing unit |
Mark Leather |
2022-04-05 |
| 11263044 |
Workload-based clock adjustment at a processing unit |
Mangesh P. Nijasure, Ashkan Hosseinzadeh Namin, Louis Regniere |
2022-03-01 |
| 11226819 |
Selective prefetching in multithreaded processing units |
Brian D. Emberling |
2022-01-18 |