Issued Patents 2022
Showing 1–17 of 17 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11528187 | Dynamically configurable networking device interfaces for directional capacity modifications | Kiran Kalkunte Seshadri, Jamie Plenderleith, Alan M. Judge, Gianluca Grilli, Alaa Adel Mahdi Hayder | 2022-12-13 |
| 11520731 | Arbitrating throttling recommendations for a systolic array | Ron Diamant | 2022-12-06 |
| 11487675 | Collecting statistics for persistent memory | — | 2022-11-01 |
| 11475306 | Processing for multiple input data sets | Dana Michelle Vantrease, Ron Diamant, Randy Renfu Huang | 2022-10-18 |
| 11467983 | Independently configurable interleaving for interconnect access requests | Mark Anthony Banse | 2022-10-11 |
| 11461631 | Scheduling neural network computations based on memory capacity | Dana Michelle Vantrease, Ron Diamant, Randy Renfu Huang | 2022-10-04 |
| 11442890 | On-circuit data activity monitoring for a systolic array | — | 2022-09-13 |
| 11422773 | Multiple busses within a systolic array processing element | Thomas Elmer, Kiran Kalkunte Seshadri | 2022-08-23 |
| 11416749 | Execution synchronization and tracking | Nafea Bshara | 2022-08-16 |
| 11392406 | Alternative interrupt reporting channels for microcontroller access devices | Mark Anthony Banse | 2022-07-19 |
| 11347916 | Increasing positive clock skew for systolic array critical path | Nishith Desai | 2022-05-31 |
| 11321179 | Powering-down or rebooting a device in a system fabric | Kun Xu, Ron Diamant, Mark Anthony Banse | 2022-05-03 |
| 11314635 | Tracking persistent memory usage | Mark Anthony Banse, Steven Scott Larson | 2022-04-26 |
| 11308026 | Multiple busses interleaved in a systolic array | Vasanta Kumar Palisetti, Thomas Elmer, Kiran Kalkunte Seshadri, Fnu Arun Kumar | 2022-04-19 |
| 11308027 | Multiple accumulate busses in a systolic array | Sundeep Amirineni, Thomas Elmer | 2022-04-19 |
| 11281967 | Event-based device performance monitoring | Nafea Bshara | 2022-03-22 |
| 11232062 | Parallelism within a systolic array using multiple accumulate busses | Sundeep Amirineni, Thomas Elmer | 2022-01-25 |