| 11194729 |
Victim cache that supports draining write-miss entries |
Timothy David Anderson, Pete Michael Hippleheuser |
2021-12-07 |
| 11157278 |
Histogram operation |
Duc Quang Bui, Rama Venkatasubramanian, Dheera Balasubramanian Samudrala, Alan L. Davis |
2021-10-26 |
| 11144456 |
Hardware coherence signaling protocol |
Abhijeet Ashok Chachad, David Matthew Thompson, Peter Michael Hippleheuser |
2021-10-12 |
| 11119935 |
Methods and apparatus to facilitate atomic compare and swap in cache for a coherent level 1 data cache system |
Timothy David Anderson, Pete Michael Hippleheuser |
2021-09-14 |
| 11106584 |
Hardware coherence for memory controller |
Abhijeet Ashok Chachad, David Matthew Thompson |
2021-08-31 |
| 11106583 |
Shadow caches for level 2 cache controller |
Abhijeet Ashok Chachad, David Matthew Thompson |
2021-08-31 |
| 11036648 |
Highly integrated scalable, flexible DSP megamodule architecture |
Timothy David Anderson, Joseph Zbiciak, Duc Quang Bui, Abhijeet Ashok Chachad, Kai Chirca +3 more |
2021-06-15 |
| 10963255 |
Implied fence on stream open |
Kai Chirca, Timothy David Anderson, Duc Quang Bui, Abhijeet Ashok Chachad, Son Hung Tran |
2021-03-30 |