| 11194617 |
Merging data for write allocate |
David Matthew Thompson |
2021-12-07 |
| 11169924 |
Prefetch management in a hierarchical cache system |
Bipin Prasad Heremagalur Ramaprasad, David Matthew Thompson, Hung Ong |
2021-11-09 |
| 11144456 |
Hardware coherence signaling protocol |
David Matthew Thompson, Naveen Bhoria, Peter Michael Hippleheuser |
2021-10-12 |
| 11138117 |
Memory pipeline control in a hierarchical memory system |
Timothy David Anderson, Kai Chirca, David Matthew Thompson |
2021-10-05 |
| 11119776 |
Cache management operations using streaming engine |
Joseph Zbiciak, Timothy David Anderson, Jonathan (Son) Hung Tran, Kai Chirca, Daniel Wu +1 more |
2021-09-14 |
| 11106584 |
Hardware coherence for memory controller |
David Matthew Thompson, Naveen Bhoria |
2021-08-31 |
| 11106583 |
Shadow caches for level 2 cache controller |
David Matthew Thompson, Naveen Bhoria |
2021-08-31 |
| 11036648 |
Highly integrated scalable, flexible DSP megamodule architecture |
Timothy David Anderson, Joseph Zbiciak, Duc Quang Bui, Kai Chirca, Naveen Bhoria +3 more |
2021-06-15 |
| 10963255 |
Implied fence on stream open |
Naveen Bhoria, Kai Chirca, Timothy David Anderson, Duc Quang Bui, Son Hung Tran |
2021-03-30 |