Issued Patents 2021
Showing 1–13 of 13 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11211388 | Array boundfary structure to reduce dishing | Te-Hsin Chiu, Wei-Cheng Wu, Li-Feng Teng, Chien-Hung Chang | 2021-12-28 |
| 11211297 | Method for testing bridging in adjacent semiconductor devices and test structure | Chia-Lin LIANG, Chih-Ren Hsieh | 2021-12-28 |
| 11195834 | Semiconductor device having deep wells | Chih-Ren Hsieh, Chen-Chin Liu | 2021-12-07 |
| 11088040 | Cell-like floating-gate test structure | Chih-Ren Hsieh, Ya-Chen Kao, Chen-Chin Liu, Chih-Pin Huang | 2021-08-10 |
| 11069693 | Method for improving control gate uniformity during manufacture of processors with embedded flash memory | Wei-Cheng Wu | 2021-07-20 |
| 11069714 | Boundary scheme for semiconductor integrated circuit and method for forming an integrated circuit | Te-An Chen | 2021-07-20 |
| 11069773 | Contact-to-gate monitor pattern and fabrication thereof | Chih-Ren Hsieh | 2021-07-20 |
| 11063044 | Metal gate modulation to improve kink effect | Te-Hsin Chiu, Wei-Cheng Wu | 2021-07-13 |
| 11031409 | Cell boundary structure for embedded memory | Chih-Ren Hsieh, Wei-Cheng Wu, Chih-Pin Huang | 2021-06-08 |
| 11031294 | Semiconductor device and a method for fabricating the same | Chih-Ren Hsieh, Chen-Chin Liu | 2021-06-08 |
| 10998315 | Metal gate modulation to improve kink effect | Te-Hsin Chiu, Wei-Cheng Wu | 2021-05-04 |
| 10971590 | Transistor layout to reduce kink effect | Te-Hsin Chiu, Wei-Cheng Wu | 2021-04-06 |
| 10937879 | Semiconductor device and manufacturing method thereof | Wei-Cheng Wu, Te-Hsin Chiu | 2021-03-02 |