JL

Jhon Jhy Liaw

TSMC: 64 patents #3 of 3,494Top 1%
📍 Dashulong, TW: #1 of 190 inventorsTop 1%
Overall (2021): #156 of 548,734Top 1%
64
Patents 2021

Issued Patents 2021

Showing 26–50 of 64 patents

Patent #TitleCo-InventorsDate
11087831 Gate-all-around memory devices 2021-08-10
11075203 Semiconductor structure 2021-07-27
11075208 IC including standard cells and SRAM cells 2021-07-27
11069692 FinFET SRAM cells with dielectric fins 2021-07-20
11063053 Integrated circuit and static random access memory thereof 2021-07-13
11063032 Semiconductor device layout 2021-07-13
11056394 Methods for fabricating FinFETs having different fin numbers and corresponding FinFETs thereof 2021-07-06
11049554 SRAM array 2021-06-29
11043501 Embedded SRAM and methods of forming the same 2021-06-22
11043490 Semiconductor device having a dielectric dummy gate 2021-06-22
11037831 Gate structure and method Ta-Chun Lin, Buo-Chin Hsu, Kuo-Hua Pan, Chih-Yung Lin 2021-06-15
11037934 SRAM circuits with aligned gate electrodes Fang Chen, Min-Chang Liang, Ren-Fen Tsui, Shih-Chi Fu, Yen-Huei Chen 2021-06-15
11031073 SRAM cells with vertical gate-all-round MOSFETs 2021-06-08
11031397 Multi-gate device integration with separated Fin-like field effect transistor cells and gate-all-around transistor cells 2021-06-08
11031074 Dual port SRAM cell with dummy transistors 2021-06-08
11031055 Memory macro and method of operating the same Chien-Kuo Su, Cheng Hung Lee, Chiting Cheng, Hung-Jen Liao, Jonathan Tsung-Yung Chang +2 more 2021-06-08
11024549 Semiconductor device and manufacturing method thereof 2021-06-01
11024632 Semiconductor structure for SRAM cell 2021-06-01
11018144 Anti-fuse cell and chip having anti-fuse cells 2021-05-25
11011636 Fin field effect transistor (FinFET) device structure with hard mask layer over gate structure and method for forming the same Cheng-Han Wu, Yu-Ho Chiang, Jyh-Huei Chen 2021-05-18
11004852 Semiconductor structure 2021-05-11
10998310 Fins with wide base in a FINFET 2021-05-04
10998237 Gate structure and method with dielectric gates and gate-cut features Ta-Chun Lin, Buo-Chin Hsu, Kuo-Hua Pan, Chih-Yung Lin 2021-05-04
10984856 Circuit for reducing voltage degradation caused by parasitic resistance in a memory device 2021-04-20
10978460 Semiconductor structure 2021-04-13