Issued Patents 2021
Showing 1–21 of 21 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11188327 | Memory lookup computing mechanisms | Peng Gu, Krishna T. Malladi | 2021-11-30 |
| 11188471 | Cache coherency for host-device systems | Lide Duan, Dimin Niu, Hongyu Liu, Shuangchen Li | 2021-11-30 |
| 11175853 | Systems and methods for write and flush support in hybrid memory | Mu-Tien Chang, Dimin Niu, Heehyun Nam, Youngjin Cho, Sun-Young Lim | 2021-11-16 |
| 11151006 | HBM RAS cache architecture | Dimin Niu, Krishna T. Malladi | 2021-10-19 |
| 11138135 | Scale-out high bandwidth memory system | Krishna T. Malladi, Dimin Niu, Peng Gu | 2021-10-05 |
| 11126354 | Effective transaction table with page bitmap | Dongyan Jiang | 2021-09-21 |
| 11119677 | HBM based memory lookup engine for deep learning accelerator | Peng Gu, Krishna T. Malladi | 2021-09-14 |
| 11100193 | Dataflow accelerator architecture for general matrix-matrix multiplication and tensor computation in deep learning | Peng Gu, Krishna T. Malladi, Dimin Niu | 2021-08-24 |
| 11099750 | Computing system with communication mechanism | Chaohong Hu, Liang Yin | 2021-08-24 |
| 11079936 | 3-D stacked memory with reconfigurable compute logic | Mu-Tien Chang, Prasun Gera, Dimin Niu | 2021-08-03 |
| 11079954 | Embedded reference counter and special data pattern auto-detect | Dongyan Jiang, Qiang Peng, Andrew Chang | 2021-08-03 |
| 11029879 | Page size synchronization and page size aware scheduling method for non-volatile memory dual in-line memory module (NVDIMM) over memory channel | Dimin Niu, Mu-Tien Chang, Sun-Young Lim, Jae Gon Lee, Indong Kim | 2021-06-08 |
| 11030088 | Pseudo main memory system | Krishna T. Malladi, Jongmin Gim | 2021-06-08 |
| 11010242 | DRAM assist error correction mechanism for DDR SDRAM interface | Dimin Niu, Mu-Tien Chang, Hyun-Joong Kim, Won-Hyung Song, Jangseok Choi | 2021-05-18 |
| 10978134 | Method and device for refreshing memory | Dimin Niu, Shuangchen Li | 2021-04-13 |
| 10977118 | DRAM assist error correction mechanism for DDR SDRAM interface | Dimin Niu, Mu-Tien Chang, Hyun-Joong Kim, Won-Hyung Song, Jangseok Choi | 2021-04-13 |
| 10929026 | Multi-cell structure for non-volatile resistive memory | Dimin Niu, Mu-Tien Chang | 2021-02-23 |
| 10915451 | Bandwidth boosted stacked memory | Krishna T. Malladi, Mu-Tien Chang, Dimin Niu | 2021-02-09 |
| 10908820 | Host-based and client-based command scheduling in large bandwidth memory systems | Krishna T. Malladi, Robert Brennan | 2021-02-02 |
| 10908993 | Method to deliver in-DRAM ECC information through DDR bus | Dimin Niu, Mu-Tien Chang, Hyun-Joong Kim, Won-Hyung Song, Jangseok Choi | 2021-02-02 |
| 10891241 | Cache memory that supports tagless addressing | Trung Diep | 2021-01-12 |