| 11188334 |
Obsoleting values stored in registers in a processor based on processing obsolescent register-encoded instructions |
Thomas Andrew Sartorius, Michael Scott McIlvaine, James Norris Dieffenderfer, Rodney Wayne Smith |
2021-11-30 |
| 11126437 |
Load instruction with final read indicator field to invalidate a buffer or cache entry storing the memory address holding load data |
Thomas Andrew Sartorius, Michael Scott McIlvaine, James Norris Dieffenderfer |
2021-09-21 |
| 11119770 |
Performing atomic store-and-invalidate operations in processor-based devices |
Eric F. Robinson |
2021-09-14 |
| 11061822 |
Method, apparatus, and system for reducing pipeline stalls due to address translation misses |
Pritha Ghoshal, Niket K. Choudhary, Ravi Rajagopalan, Patrick Eibl, Brian Michael Stempel +1 more |
2021-07-13 |
| 11061820 |
Optimizing access to page table entries in processor-based devices |
— |
2021-07-13 |
| 11016899 |
Selectively honoring speculative memory prefetch requests based on bandwidth state of a memory access path component(s) in a processor-based system |
Nikhil Narendradev Sharma, Eric F. Robinson, Garrett M. Drapala, Perry Willmann Remaklus, Jr., Joseph Gerald McDonald |
2021-05-25 |
| 10956162 |
Operand-based reach explicit dataflow processors, and related methods and computer-readable media |
Robert Douglas Clancy, Melinda J. Brown, Yusuf Cagatay Tekmen, Brian Michael Stempel, Michael Scott McIlvaine +3 more |
2021-03-23 |
| 10896135 |
Facilitating page table entry (PTE) maintenance in processor-based devices |
Eric F. Robinson, Jason Panavich |
2021-01-19 |
