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Multi-function unit for programmable hardware nodes for neural network processing |
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Decoupled processor instruction window and operand buffer |
Aaron L. Smith, Jan Gray |
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Distinct system registers for logical processors |
Aaron L. Smith |
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Data processing system having a hardware acceleration plane and a software plane |
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Partially reconfiguring acceleration components |
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Coupling wide memory interface to wide write back paths |
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Dense read encoding for dataflow ISA |
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2021-03-02 |
