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William Robert Reece

CS Cadence Design Systems: 6 patents #4 of 250Top 2%
📍 Bradley Stoke, CA: #1 of 1 inventorsTop 100%
Overall (2021): #19,113 of 548,734Top 4%
6
Patents 2021

Issued Patents 2021

Showing 1–6 of 6 patents

Patent #TitleCo-InventorsDate
11188702 Dynamic weighting scheme for local cluster refinement Bentian Jiang, Natarajan Viswanathan, Zhuo Li 2021-11-30
11163929 Generate clock network using inverting integrated clock gate Thomas Andrew Newton, Ruth Patricia Jackson, Zhuo Li 2021-11-02
11132490 Using negative-edge integrated clock gate in clock network Ruth Patricia Jackson, Thomas Andrew Newton, Zhuo Li 2021-09-28
10990721 Delay dependence in physically aware cell cloning Thomas Andrew Newton, Zhuo Li 2021-04-27
10963617 Modifying route topology to fix clock tree violations Andrew Mark Chapman, Natarajan Viswanathan, Mehmet Can Yildiz, Gracieli Posser, Zhuo Li 2021-03-30
10963618 Multi-dimension clock gate design in clock tree synthesis Amin Farshidi, Kwangsoo Han, Thomas Andrew Newton, Zhuo Li 2021-03-30