Issued Patents 2021
Showing 1–16 of 16 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11188702 | Dynamic weighting scheme for local cluster refinement | Bentian Jiang, Natarajan Viswanathan, William Robert Reece | 2021-11-30 |
| 11163929 | Generate clock network using inverting integrated clock gate | William Robert Reece, Thomas Andrew Newton, Ruth Patricia Jackson | 2021-11-02 |
| 11132490 | Using negative-edge integrated clock gate in clock network | Ruth Patricia Jackson, William Robert Reece, Thomas Andrew Newton | 2021-09-28 |
| 11132489 | Layer assignment based on wirelength threshold | Derong Liu, Yi-Xiao Ding, Mehmet Can Yildiz | 2021-09-28 |
| 11080457 | Layer assignment and routing based on resistance or capacitance characteristic | Derong Liu, Yi-Xiao Ding, Mehmet Can Yildiz | 2021-08-03 |
| 11030378 | Track assignment by dynamic programming | Yi-Xiao Ding, Mehmet Can Yildiz | 2021-06-08 |
| 10997352 | Routing congestion based on layer-assigned net and placement blockage | Gracieli Posser, Mehmet Can Yildiz, Wen-Hao Liu, Wing-Kai Chow, Derong Liu | 2021-05-04 |
| 10990721 | Delay dependence in physically aware cell cloning | William Robert Reece, Thomas Andrew Newton | 2021-04-27 |
| 10963620 | Buffer insertion technique to consider edge spacing and stack via design rules | Yi-Xiao Ding, Jhih-Rong Gao | 2021-03-30 |
| 10963618 | Multi-dimension clock gate design in clock tree synthesis | Amin Farshidi, William Robert Reece, Kwangsoo Han, Thomas Andrew Newton | 2021-03-30 |
| 10963617 | Modifying route topology to fix clock tree violations | Andrew Mark Chapman, William Robert Reece, Natarajan Viswanathan, Mehmet Can Yildiz, Gracieli Posser | 2021-03-30 |
| 10936783 | Runtime efficient circuit placement search location selection | Andrew Mark Chapman | 2021-03-02 |
| 10936777 | Unified improvement scoring calculation for rebuffering an integrated circuit design | Jhih-Rong Gao, Yi-Xiao Ding | 2021-03-02 |
| 10929589 | Generating routing structure for clock network based on edge intersection detection | Dirk Meyer | 2021-02-23 |
| 10885257 | Routing congestion based on via spacing and pin density | Gracieli Posser, Wing-Kai Chow, Mehmet Can Yildiz | 2021-01-05 |
| 10885250 | Clock gate placement with data path awareness | David White, Andrew Mark Chapman, Thomas Andrew Newton | 2021-01-05 |