Issued Patents 2021
Showing 1–14 of 14 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11188341 | System, apparatus and method for symbolic store address generation for data-parallel processor | Jeffrey J. Cook, Jonathan Pearce, David Sheffield | 2021-11-30 |
| 11182158 | Technologies for providing adaptive memory media management | Bruce Querbach, Shigeki Tomishima, Chetan Chauhan, Rajesh Sundaram | 2021-11-23 |
| 11139807 | Buffer circuit | Rajat Chauhan | 2021-10-05 |
| 11126438 | System, apparatus and method for a hybrid reservation station for a processor | Thomas Mullins, Ammon Christiansen, James Hadley, Robert S. Chappell, Sean P. Mirkes | 2021-09-21 |
| 11093250 | Apparatus and method for gang invariant operation optimizations using dynamic evaluation | Jonathan Pearce, David Sheffield, Jaewoong Sim, Andrey Ayupov | 2021-08-17 |
| 11093442 | Non-disruptive and efficient migration of data across cloud providers | Neeraj Bhutani, Ramprasad Chinthekindi, Nitin Madan | 2021-08-17 |
| 11080226 | Technologies for providing a scalable architecture for performing compute operations in memory | Shigeki Tomishima, Chetan Chauhan, Rajesh Sundaram, Jawad B. Khan | 2021-08-03 |
| 11063580 | Input buffer with wide range of I/O voltage level | Pranshu Kalra, Devraj Matharampallil Rajagopal | 2021-07-13 |
| 11023320 | Technologies for providing multiple levels of error correction | Wei Wu, Rajesh Sundaram, Chetan Chauhan, Jawad B. Khan, Shigeki Tomishima | 2021-06-01 |
| 10956160 | Method and apparatus for a multi-level reservation station with instruction recirculation | Mark Dechene, Matthew C. Merten, Ammon Christiansen | 2021-03-23 |
| 10929176 | Method of efficiently migrating data from one tier to another with suspend and resume capability | Ramprasad Chinthekindi, Abhinav Duggal, Lan Bai | 2021-02-23 |
| 10924095 | Multi-resonant coupling architectures for ZZ interaction reduction | David C. Mckay, Abhinav Kandala | 2021-02-16 |
| 10915328 | Apparatus and method for a high throughput parallel co-processor and interconnect with low offload latency | Jonathan Pearce, David Sheffield, Jeffrey J. Cook, Deborah T. Marr | 2021-02-09 |
| 10896141 | Gather-scatter cache architecture having plurality of tag and data banks and arbiter for single program multiple data (SPMD) processor | Jeffrey J. Cook, Jonathan Pearce, Rishiraj A. Bheda, David Sheffield, Abhijit Davare +1 more | 2021-01-19 |