Issued Patents 2021
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11182240 | Techniques to improve error correction using an XOR rebuild scheme of multiple codewords and prevent miscorrection from read reference voltage shifts | Santhosh K. Vanaparthy, Zion S. Kwok | 2021-11-23 |
| 11159175 | Non-uniform iteration-dependent min-sum scaling factors for improved performance of spatially-coupled LDPC codes | Santhosh K. Vanaparthy | 2021-10-26 |
| 11086714 | Permutation of bit locations to reduce recurrence of bit error patterns in a memory device | Zion S. Kwok | 2021-08-10 |
| 10942799 | Defective bit line management in connection with a memory access | Ali Khakifirooz, Pranav Kalavade, Chang Wan Ha | 2021-03-09 |
| 10944428 | Device, system and method for determining bit reliability information | Poovaiah M. Palangappa, Santhosh K. Vanaparthy | 2021-03-09 |
| 10908996 | Distribution of a codeword across individual storage units to reduce the bit error rate | — | 2021-02-02 |