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Machine learning training architecture for programmable devices |
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Integrated circuits with machine learning extensions |
Dongdong Chen |
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Programmable-logic-directed multiplier mapping |
Gregg William Baeckler |
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| 11137983 |
Programmable device implementing fixed and floating point functionality in a mixed architecture |
Keone Streicher, Yi-Wen Lin, Hyun Yi |
2021-10-05 |
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Decomposable forward error correction |
Peng Li, Masashi Shimanouchi |
2021-08-24 |
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Method and apparatus for performing synthesis for field programmable gate array embedded feature placement |
Gregg William Baeckler, Sergey Gribok |
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Continuous carry-chain packing |
Sergey Gribok, Gregg William Baeckler |
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High radix subset code multiplier architecture |
Gregg William Baeckler |
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Floating-point adder circuitry with subnormal support |
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Reduction operation mapping systems and methods |
Gregg William Baeckler, Bogdan Pasca |
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Variable precision floating-point multiplier |
— |
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Security RAM block with multiple partitions |
— |
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Integrated circuits with machine learning extensions |
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Implementation of floating-point trigonometric functions in an integrated circuit device |
Bogdan Pasca |
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| 10922471 |
High performance regularized network-on-chip architecture |
Gregg William Baeckler, Sergey Gribok |
2021-02-16 |