Issued Patents 2021
Showing 76–100 of 113 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11030104 | Picket fence staging in a multi-tier cache | Kevin J. Ash, Kyler A. Anderson, Matthew G. Borlick | 2021-06-08 |
| 11030116 | Processing cache miss rates to determine memory space to add to an active cache to reduce a cache miss rate for the active cache | Kyler A. Anderson, Kevin J. Ash, Matthew G. Borlick | 2021-06-08 |
| 11029849 | Handling cache and non-volatile storage (NVS) out of sync writes | Kyler A. Anderson, Kevin J. Ash, Beth A. Peterson | 2021-06-08 |
| 11023383 | Cache management based on types of I/O operations | Kyler A. Anderson, Kevin J. Ash | 2021-06-01 |
| 11025518 | Communicating health status when a management console is unavailable | Matthew G. Borlick, Micah Robison | 2021-06-01 |
| 11023029 | Preventing unexpected power-up failures of hardware components | Matthew G. Borlick, Brian J. Cagno, Karl A. Nielsen, Todd C. Sorenson | 2021-06-01 |
| 11016851 | Determine recovery mechanism in a storage system by training a machine learning module | Brian A. Rinaldi, Clint A. Hardy | 2021-05-25 |
| 11016692 | Dynamically switching between memory copy and memory mapping to optimize I/O performance | Kevin J. Ash, Brian A. Rinaldi, Kyler A. Anderson, Matthew J. Kalos | 2021-05-25 |
| 11010248 | Reuse of resources in a storage controller for executing write commands over a plurality of interfaces | Beth A. Peterson, Kevin J. Ash, Chung Man Fung | 2021-05-18 |
| 11010295 | Asynchronous update of metadata tracks in response to a cache hit generated via an i/o operation over a bus interface | Kyler A. Anderson, Kevin J. Ash, Matthew J. Kalos | 2021-05-18 |
| 11003777 | Determining a frequency at which to execute trap code in an execution path of a process executing a program to generate a trap address range to detect potential malicious code | Matthew G. Borlick, Trung N. Nguyen, Micah Robison | 2021-05-11 |
| 11003496 | Performance-based multi-mode task dispatching in a multi-processor core system for high temperature avoidance | Matthew G. Borlick, Trung N. Nguyen | 2021-05-11 |
| 10996891 | Token management for write commands transmitted by a host over a plurality of interfaces to a storage controller | Beth A. Peterson, Kevin J. Ash, Chung Man Fung | 2021-05-04 |
| 10990481 | Using alternate recovery actions for initial recovery actions in a computing system | Matthew G. Borlick, Karl A. Nielsen | 2021-04-27 |
| 10983885 | Recovering storage devices in a storage array having errors | Brian J. Cagno, John C. Elliott, Matthew G. Borlick, Will A. Wright | 2021-04-20 |
| 10983922 | Selecting one of multiple cache eviction algorithms to use to evict a track from the cache using a machine learning module | Matthew G. Borlick, Kyler A. Anderson, Kevin J. Ash | 2021-04-20 |
| 10983913 | Securing exclusive access to a copy of a metadata track via a process while the metadata track is held in a shared mode by another process | Kyler A. Anderson, Kevin J. Ash, Matthew J. Kalos, Beth A. Peterson | 2021-04-20 |
| 10983836 | Transaction optimization during periods of peak activity | Matthew G. Borlick, John C. Elliott | 2021-04-20 |
| 10976941 | Validation of storage volumes that are in a peer to peer remote copy relationship | Matthew G. Borlick, Brian A. Rinaldi, Micah Robison | 2021-04-13 |
| 10976940 | Copy source to target management in a data storage system | Kevin J. Ash, Clint A. Hardy, Karl A. Nielsen | 2021-04-13 |
| 10970209 | Destaging metadata tracks from cache | Kevin J. Ash, Kyler A. Anderson, Matthew G. Borlick | 2021-04-06 |
| 10963386 | Dynamically determining tracks to prestage from storage to cache by training a machine learning module | Kyler A. Anderson, Matthew G. Borlick, Kevin J. Ash | 2021-03-30 |
| 10956322 | Storage drive dependent track removal in a cache for storage | Kevin J. Ash, Matthew G. Borlick, Trung N. Nguyen | 2021-03-23 |
| 10956046 | Dynamic I/O load balancing for zHyperLink | Kevin J. Ash, Matthew G. Borlick, Kyler A. Anderson | 2021-03-23 |
| 10949277 | Monitoring correctable errors on a bus interface to determine whether to redirect input/output (I/O) traffic from a first processing unit to a second processing unit | Matthew G. Borlick, Trung N. Nguyen | 2021-03-16 |