| 11205005 |
Identifying microarchitectural security vulnerabilities using simulation comparison with modified secret data |
Matthew Michael Garcia Pardini, Gregory W. Alexander, Michael P. Mullen, Olaf K. Hendrickson |
2021-12-21 |
| 11150902 |
Processor pipeline management during cache misses using next-best ticket identifier for sleep and wakeup |
Taylor J. Pritchard, Michael J. Cadigan, Jr. |
2021-10-19 |
| 11144321 |
Store hit multiple load side register for preventing a subsequent store memory violation |
Yair Fried, Eyal Naor, James J. Bonanno, Gregory W. Alexander |
2021-10-12 |
| 11144367 |
Write power optimization for hardware employing pipe-based duplicate register files |
Richard Joseph Branciforte, Gregory W. Alexander, Avraham Ayzenfeld, Edward T. Malley, Gregory Miaskovsky |
2021-10-12 |
| 11080199 |
Determining logical address of an oldest memory access request |
Yossi Shapira, Michael J. Cadigan, Jr., Jane H. Bartik, Taylor J. Pritchard |
2021-08-03 |
| 11074184 |
Maintaining data order between buffers |
Michael J. Cadigan, Jr., Erez Barak, Deepankar Bhattacharjee, Yair Fried, Martin Recktenwald +1 more |
2021-07-27 |
| 10963259 |
Accounting for multiple pipeline depths in processor instrumentation |
Avery Francois, Gregory W. Alexander |
2021-03-30 |
| 10929142 |
Making precise operand-store-compare predictions to avoid false dependencies |
Gregory W. Alexander, James J. Bonanno, Adam B. Collura, James R. Cuffney, Yair Fried +4 more |
2021-02-23 |
