| 11157281 |
Prefetching data based on register-activity patterns |
Yossi Shapira, Yair Fried, Amir Turi |
2021-10-26 |
| 11144321 |
Store hit multiple load side register for preventing a subsequent store memory violation |
Yair Fried, Jonathan T. Hsieh, James J. Bonanno, Gregory W. Alexander |
2021-10-12 |
| 11029950 |
Reducing latency of common source data movement instructions |
Yossi Shapira, Yair Fried, Amir Turi |
2021-06-08 |
| 10977040 |
Heuristic invalidation of non-useful entries in an array |
James R. Cuffney, Adam B. Collura, James J. Bonanno, Jang-Soo Lee, Yair Fried +1 more |
2021-04-13 |
| 10970214 |
Selective downstream cache processing for data access |
Willm Hinrichs, Markus Kaltenbach, Martin Recktenwald |
2021-04-06 |
| 10956328 |
Selective downstream cache processing for data access |
Willm Hinrichs, Markus Kaltenbach, Martin Recktenwald |
2021-03-23 |
| 10929142 |
Making precise operand-store-compare predictions to avoid false dependencies |
Gregory W. Alexander, James J. Bonanno, Adam B. Collura, James R. Cuffney, Yair Fried +4 more |
2021-02-23 |
