Issued Patents 2021
Showing 1–25 of 39 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11182293 | Operating different processor cache levels | Simon H. Friedmann, Markus Kaltenbach, Ulrich Mayer, Anthony Saporito | 2021-11-23 |
| 11182168 | Post completion execution in an out-of-order processor design | Avery Francois, Gregory W. Alexander | 2021-11-23 |
| 11175923 | Comparing load instruction address fields to store instruction address fields in a table to delay issuing dependent load instructions | Gregory W. Alexander, James J. Bonanno, Adam B. Collura, Bruce C. Giamei, Jang-Soo Lee +3 more | 2021-11-16 |
| 11169922 | Method and arrangement for saving cache power | Markus Kaltenbach, Ulrich Mayer, Johannes C. Reichart, Anthony Saporito, Siegmund Schlechter | 2021-11-09 |
| 11163566 | Handling an input/output store instruction | Christoph Raisch, Marco Kraemer, Frank Lehnert, Matthias Klein, Jonathan D. Bradbury +2 more | 2021-11-02 |
| 11157240 | Perform cryptographic computation scalar multiply instruction | Eric M. Schwarz, Jonathan D. Bradbury, Edward T. Malley | 2021-10-26 |
| 11108567 | Compute digital signature authentication verify instruction | Eric M. Schwarz, Jonathan D. Bradbury, Edward T. Malley | 2021-08-31 |
| 11080087 | Transaction begin/end instructions | Dan F. Greiner, Marcel Mitran, Timothy J. Slegel | 2021-08-03 |
| 11080064 | Instructions controlling access to shared registers of a multi-threaded processor | Giora Biran, Fadi Y. Busaba, Ophir Erez, Mark S. Farrell, Lisa C. Heller +2 more | 2021-08-03 |
| 11080052 | Determining the effectiveness of prefetch instructions | Michael K. Gschwind, Anthony Saporito, Chung-Lung K. Shum, Timothy J. Slegel | 2021-08-03 |
| 11074203 | Handling an input/output store instruction | Christoph Raisch, Marco Kraemer, Frank Lehnert, Matthias Klein, Jonathan D. Bradbury +2 more | 2021-07-27 |
| 11075763 | Compute digital signature authentication sign with encrypted key instruction | Eric M. Schwarz, Jonathan D. Bradbury, Edward T. Malley | 2021-07-27 |
| 11068303 | Adjusting thread balancing in response to disruptive complex instruction | Avery Francois, Gregory W. Alexander | 2021-07-20 |
| 11068266 | Handling an input/output store instruction | Christoph Raisch, Marco Kraemer, Frank Lehnert, Matthias Klein, Jonathan D. Bradbury +2 more | 2021-07-20 |
| 11061680 | Instructions controlling access to shared registers of a multi-threaded processor | Giora Biran, Fadi Y. Busaba, Ophir Erez, Mark S. Farrell, Lisa C. Heller +2 more | 2021-07-13 |
| 11048475 | Multi-cycle key compares for keys and records of variable length | Norbert Hagspiel, Jörg-Stephan Vogt, Thomas Fuchs | 2021-06-29 |
| 11048635 | Controlling a rate of prefetching based on bus bandwidth | Jonathan D. Bradbury, Michael K. Gschwind, Chung-Lung K. Shum | 2021-06-29 |
| 11010276 | Configurable code fingerprint | Giles R. Frazier, Michael K. Gschwind, Chung-Lung K. Shum | 2021-05-18 |
| 11010066 | Identifying processor attributes based on detecting a guarded storage event | Dan F. Greiner, Marcel Mitran, Volodymyr Paprotski, Anthony Saporito, Timothy J. Slegel | 2021-05-18 |
| 11010168 | Effectiveness and prioritization of prefetches | Michael K. Gschwind, Anthony Saporito, Chung-Lung K. Shum | 2021-05-18 |
| 11010298 | Reducing cache transfer overhead in a system | Christian Zoellin, Chung-Lung K. Shum, Martin Recktenwald, Anthony Saporito, Aaron Tsai | 2021-05-18 |
| 11010307 | Cache management | Deanna Postles Dunn Berger, Martin Recktenwald, Yossi Shapira, Aaron Tsai | 2021-05-18 |
| 11003452 | Effectiveness and prioritization of prefetches | Michael K. Gschwind, Anthony Saporito, Chung-Lung K. Shum | 2021-05-11 |
| 10997079 | Method and arrangement for saving cache power | Markus Kaltenbach, Ulrich Mayer, Johannes C. Reichart, Anthony Saporito, Siegmund Schlechter | 2021-05-04 |
| 10983833 | Virtualized and synchronous access to hardware accelerators | Brenton F. Belmar, Matthias Klein, Peter G. Sutton | 2021-04-20 |