PT

Phung Truong

CS Cadence Design Systems: 2 patents #23 of 250Top 10%
📍 San Jose, CA: #1,570 of 6,693 inventorsTop 25%
🗺 California: #13,721 of 66,859 inventorsTop 25%
Overall (2021): #122,557 of 548,734Top 25%
2
Patents 2021

Issued Patents 2021

Showing 1–2 of 2 patents

Patent #TitleCo-InventorsDate
11156660 In-system scan test of electronic devices Mitchell G. Poplack, Xiaolei Guo, Justin Schmelzer 2021-10-26
10997343 In-system scan test of chips in an emulation system Mitchell G. Poplack, Xiaolei Guo, Justin Schmelzer 2021-05-04