Issued Patents 2020
Showing 1–5 of 5 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10725934 | Processor with selective data storage (of accelerator) operable as either victim cache data storage or accelerator memory and having victim cache tags in lower level cache wherein evicted cache line is stored in said data storage when said data storage is in a first mode and said cache line is stored in system memory rather then said data store when said data storage is in a second mode | G. Glenn Henry, Terry Parks | 2020-07-28 |
| 10719434 | Multi-mode set associative cache memory dynamically configurable to selectively allocate into all or a subset of its ways depending on the mode | — | 2020-07-21 |
| 10698827 | Dynamic cache replacement way selection based on address tag bits | — | 2020-06-30 |
| 10664751 | Processor with memory array operable as either cache memory or neural network unit memory | G. Glenn Henry | 2020-05-26 |
| 10642617 | Processor with an expandable instruction set architecture for dynamically configuring execution resources | G. Glenn Henry, Rodney E. Hooker, Terry Parks | 2020-05-05 |