Issued Patents 2020
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10840246 | Integrated circuit having a vertical power MOS transistor | Chun-Wai Ng, Hsueh-Liang Chou, Po-Chih Su | 2020-11-17 |
| 10727334 | Lateral DMOS device with dummy gate | Chun-Wai Ng, Jun Cai, Hsueh-Liang Chou, Chi-Chih Chen | 2020-07-28 |
| 10714432 | Layout to reduce noise in semiconductor devices | Chih-Chang Cheng, Fu-Yu Chu | 2020-07-14 |
| 10686047 | Semiconductor device and method for manufacturing the same | Ta-Yuan Kung, Chen-Liang Chu, Chih-Wen Yao, Ming-Ta Lei | 2020-06-16 |
| 10686032 | High voltage resistor with high voltage junction termination | Ru-Yi Su, Fu-Chih Yang, Chun Lin Tsai, Chih-Chang Cheng | 2020-06-16 |
| 10686065 | Apparatus and method for power MOS transistor | Chun-Wai Ng, Hsueh-Liang Chou, Po-Chih Su | 2020-06-16 |
| 10680100 | Field structure and methodology | Po-Chih Su, Hsueh-Liang Chou | 2020-06-09 |
| 10680019 | Selective polysilicon doping for gate induced drain leakage improvement | Chen-Liang Chu, Chih-Wen Yao, Ming-Ta Lei | 2020-06-09 |
| 10672904 | Power MOSFETs and methods for manufacturing the same | Yogendra Yadav, Chi-Chih Chen, Chih-Wen Yao | 2020-06-02 |
| 10658482 | Plate design to decrease noise in semiconductor devices | Chih-Chang Cheng, Fu-Yu Chu, Ming-Ta Lei, Shih-Fen Huang | 2020-05-19 |