JB

Jaskirat Bindra

TSMC: 2 patents #1,197 of 3,471Top 35%
📍 San Jose, CA: #1,710 of 6,906 inventorsTop 25%
🗺 California: #15,013 of 68,989 inventorsTop 25%
Overall (2020): #164,813 of 565,922Top 30%
2
Patents 2020

Issued Patents 2020

Showing 1–2 of 2 patents

Patent #TitleCo-InventorsDate
10819325 Selectable delay buffers and logic cells for dynamic voltage scaling in ultra low voltage designs Kumar Lalgudi 2020-10-27
10748849 Tapering discrete interconnection for an integrated circuit (IC) Kumar Lalgudi 2020-08-18