Issued Patents 2020
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10861562 | Deep learning based regression framework for read thresholds in a NAND flash memory | Fan Zhang, Xuanxuan Lu, Meysam Asadi, Jianqing Chen | 2020-12-08 |
| 10847231 | Memory system with adaptive read-threshold scheme and method of operating such memory system | Aman Bhatia, Fan Zhang, Naveen Kumar, Yu Cai | 2020-11-24 |
| 10714195 | Read disturb detection and recovery with adaptive thresholding for 3-D NAND storage | Naveen Kumar, Aman Bhatia, Fan Zhang, Yu Cai | 2020-07-14 |
| 10707899 | Bit-flipping decoder for G-LDPC codes with syndrome-decoding for component codes | Aman Bhatia, Naveen Kumar, Fan Zhang, Xuanxuan Lu, Yu Cai | 2020-07-07 |
| 10700706 | Memory system with decoders and method of operating such memory system and decoders | Fan Zhang, Aman Bhatia, Naveen Kumar, Yu Cai | 2020-06-30 |
| 10693496 | Memory system with LDPC decoder and method of operating such memory system and LDPC decoder | Naveen Kumar, Aman Bhatia, Yu Cai, Fan Zhang | 2020-06-23 |
| 10691536 | Method to select flash memory blocks for refresh after read operations | Aman Bhatia, Fan Zhang, Naveen Kumar, Yu Cai | 2020-06-23 |
| 10691540 | Soft chip-kill recovery for multiple wordlines failure | Naveen Kumar, Aman Bhatia, Yu Cai, Fan Zhang | 2020-06-23 |
| 10680647 | Min-sum decoding for LDPC codes | Aman Bhatia, Naveen Kumar, Abhiram Prabhakar, Fan Zhang | 2020-06-09 |
| 10672497 | Memory system and method for bad block management | Yu Cai, Fan Zhang, Naveen Kumar, Aman Bhatia, Xuanxuan Lu | 2020-06-02 |
| 10601546 | Dynamic interleaver change for bit line failures in NAND flash storage | Naveen Kumar, Aman Bhatia, Yu Cai, Fan Zhang, Xuanxuan Lu | 2020-03-24 |
| 10572342 | Memory system with LDPC decoder and operating method thereof | Aman Bhatia, Naveen Kumar, Fan Zhang | 2020-02-25 |