Issued Patents 2020
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10872662 | 2T2R binary weight cell with high on/off ratio background | Ryan M. Hatcher, Titash Rakshit, Jorge A. Kittl, Rwik Sengupta, Dharmendar Reddy Palle | 2020-12-22 |
| 10868193 | Nanosheet field effect transistor cell architecture | Rwik Sengupta, Mark S. Rodder, Titash Rakshit | 2020-12-15 |
| 10861950 | Integrated circuit including field effect transistors having a contact on active gate compatible with a small cell area having a small contacted poly pitch | Rwik Sengupta, Mark S. Rodder, Titash Rakshit | 2020-12-08 |
| 10832774 | Variation resistant 3T3R binary weight cell with low output current and high on/off ratio | Ryan M. Hatcher, Titash Rakshit, Jorge A. Kittl, Rwik Sengupta, Dharmendar Reddy Palle | 2020-11-10 |
| 10825723 | Semiconductor device and method for making the same | Harsono S. Simka, Mark S. Rodder | 2020-11-03 |
| 10811415 | Semiconductor device and method for making the same | Rwik Sengupta, Vassilios Gerousis, Mark S. Rodder | 2020-10-20 |
| 10727297 | Complimentary metal-oxide-semiconductor circuit having transistors with different threshold voltages and method of manufacturing the same | Wei-E Wang | 2020-07-28 |
| 10644031 | Method for selectively increasing silicon fin area for vertical field effect transistors | Kang-ill Seo, Borna J. Obradovic | 2020-05-05 |
| 10586738 | Method of providing source and drain doping for CMOS architecture including FinFET and semiconductor devices so formed | Wei-E Wang, Mark S. Rodder, Borna J. Obradovic | 2020-03-10 |