Issued Patents 2020
Showing 1–24 of 24 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10866900 | ISA extension for high-bandwidth memory | Mu-Tien Chang, Krishna T. Malladi, Dimin Niu | 2020-12-15 |
| 10866897 | Byte-addressable flash-based memory module with prefetch mode that is adjusted based on feedback from prefetch accuracy that is calculated by comparing first decoded address and second decoded address, where the first decoded address is sent to memory controller, and the second decoded address is sent to prefetch buffer | Mu-Tien Chang, Dimin Niu, Dongyan Jiang | 2020-12-15 |
| 10853265 | Address mapping in memory systems | James Tringali | 2020-12-01 |
| 10853261 | Methods and apparatuses for addressing memory caches | Trung Diep | 2020-12-01 |
| 10824499 | Memory system architectures using a separate system control path or channel for processing error information | Chaohong Hu, Uksong Kang, Zhan Ping | 2020-11-03 |
| 10810144 | System and method for operating a DRR-compatible asynchronous memory module | Sun-Young Lim, Mu-Tien Chang, Dimin Niu, Indong Kim | 2020-10-20 |
| 10795764 | Method to deliver in-DRAM ECC information through DDR bus | Dimin Niu, Mu-Tien Chang, Hyun-Joong Kim, Won-Hyung Song, Jangseok Choi | 2020-10-06 |
| 10762000 | Techniques to reduce read-modify-write overhead in hybrid DRAM/NAND memory | Mu-Tien Chang, Heehyun Nam, Youngsik Kim, Youngjin Cho, Dimin Niu | 2020-09-01 |
| 10732929 | Computing accelerator using a lookup table | Krishna T. Malladi, Peng Gu, Robert Brennan | 2020-08-04 |
| 10732866 | Scaling out architecture for DRAM-based processing unit (DPU) | Dimin Niu, Shuangchen Li, Bob Brennan, Krishna T. Malladi | 2020-08-04 |
| 10705969 | Dedupe DRAM cache | Mu-Tien Chang, Andrew Chang, Dongyan Jiang | 2020-07-07 |
| 10705988 | Memory module threading with staggered data transfers | Frederick A. Ware | 2020-07-07 |
| 10684823 | Unsuccessful write retry buffer | Brent Haukness | 2020-06-16 |
| 10678704 | Method and apparatus for enabling larger memory capacity than physical memory size | Dongyan Jiang, Changhui Lin, Krishna T. Malladi, Jongmin Gim | 2020-06-09 |
| 10628295 | Computing mechanisms using lookup tables stored on memory | Peng Gu, Krishna T. Malladi | 2020-04-21 |
| 10628072 | Scalable architecture enabling large memory system for in-memory computations | Dongyan Jiang, Qiang Peng | 2020-04-21 |
| 10621119 | Asynchronous communication protocol compatible with synchronous DDR protocol | Dimin Niu, Mu-Tien Chang, Sun-Young Lim, Indong Kim, Jangseok Choi +1 more | 2020-04-14 |
| 10592121 | Quasi-synchronous protocol for large bandwidth memory systems | Krishna T. Malladi | 2020-03-17 |
| 10592114 | Coordinated in-module RAS features for synchronous DDR compatible memory | Mu-Tien Chang, Dimin Niu, Sun-Young Lim, Indong Kim, Jangseok Choi | 2020-03-17 |
| 10558388 | Memory system and method of controlling the same | Dimin Niu, Mu-Tien Chang, Craig Hanson, Sun-Young Lim, Indong Kim | 2020-02-11 |
| 10552256 | Morphable ECC encoder/decoder for NVDIMM over DDR channel | Dimin Niu, Mu-Tien Chang | 2020-02-04 |
| 10552042 | Effective transaction table with page bitmap | Dongyan Jiang | 2020-02-04 |
| 10545860 | Intelligent high bandwidth memory appliance | Krishna T. Malladi, Robert Brennan, Hyungseuk KIM, Jinhyun Kim | 2020-01-28 |
| 10528284 | Method and apparatus for enabling larger memory capacity than physical memory size | Dongyan Jiang, Changhui Lin, Krishna T. Malladi, Jongmin Gim | 2020-01-07 |