Issued Patents 2020
Showing 1–4 of 4 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10740526 | Integrated circuit design system with automatic timing margin reduction | Jeffrey Alan Fredenburg, David M. Moore, Ramin Shirani, Yu-Hui Huang | 2020-08-11 |
| 10713409 | Integrated circuit design system with automatic timing margin reduction | Jeffrey Alan Fredenburg, David M. Moore, Ramin Shirani, Yu-Hui Huang | 2020-07-14 |
| 10614182 | Timing analysis for electronic design automation of parallel multi-state driver circuits | Jeffrey Alan Fredenburg, David M. Moore, Ramin Shirani | 2020-04-07 |
| 10587275 | Locked loop circuit with configurable second error input | Jeffrey Alan Fredenburg | 2020-03-10 |