Issued Patents 2020
Showing 1–5 of 5 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10831958 | Integrated circuit design with optimized timing constraint configuration | Ofer Geva, Shiran Raz | 2020-11-10 |
| 10657211 | Circuit generation based on zero wire load assertions | Limor Plotkin, Shiran Raz, Ofer Geva | 2020-05-19 |
| 10572613 | Estimating timing convergence using assertion comparisons | Ofer Geva, Limor Plotkin, Shiran Raz | 2020-02-25 |
| 10568203 | Modifying a circuit design | Ofer Geva, Shiran Raz, Limor Elizov | 2020-02-18 |
| 10546092 | Modifying a circuit design based on pre-routed top level design | Ido Geldman, Ofer Geva, Rina Kipnis, Vadim Liberchuk, Asaf Regev | 2020-01-28 |