Issued Patents 2020
Showing 1–4 of 4 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10831958 | Integrated circuit design with optimized timing constraint configuration | Ofer Geva, Yaniv Maroz | 2020-11-10 |
| 10657211 | Circuit generation based on zero wire load assertions | Limor Plotkin, Yaniv Maroz, Ofer Geva | 2020-05-19 |
| 10572613 | Estimating timing convergence using assertion comparisons | Ofer Geva, Yaniv Maroz, Limor Plotkin | 2020-02-25 |
| 10568203 | Modifying a circuit design | Ofer Geva, Limor Elizov, Yaniv Maroz | 2020-02-18 |