Issued Patents 2020
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10878860 | Multi-level signaling scheme for memory interface | Shiv Harit Mathur, Ramakrishnan Subramanian | 2020-12-29 |
| 10862487 | Locked loop circuit with reference signal provided by un-trimmed oscillator | Anand Kumar, Nitin Jain | 2020-12-08 |
| 10861508 | Transmitting DBI over strobe in nonvolatile memory | Shiv Harit Mathur, Ramakrishnan Subramanian | 2020-12-08 |
| 10838901 | System and method for a reconfigurable controller bridge chip | Vijay Chinchole, Siva Raghu Ram Voleti, Ramakrishnan Subramanian, Shiv Harit Mathur, Yan Li +1 more | 2020-11-17 |
| 10840915 | Use of a raw oscillator and frequency locked loop to quicken lock time of frequency locked loop | Jeet Narayan Tiwari | 2020-11-17 |
| 10795389 | Low leakage low dropout regulator with high bandwidth and power supply rejection, and associated methods | Kapil Kumar Tyagi | 2020-10-06 |
| 10771073 | Frequency synthesizer with dynamically selected level shifting of the oscillating output signal | — | 2020-09-08 |
| 10635843 | Simulation modeling frameworks for controller designs | Amit Garg, Ashutosh Pandey | 2020-04-28 |
| 10615809 | Calibration of a voltage controlled oscillator to trim the gain thereof, using a phase locked loop and a frequency locked loop | Ankit Gupta, Anand Kumar | 2020-04-07 |
| 10566980 | Use of a raw oscillator and frequency locked loop to quicken lock time of frequency locked loop | Jeet Narayan Tiwari | 2020-02-18 |
| 10544109 | Process for the preparation of xylene linked cyclam compounds | Hemant Kumar Singh, Sandeep Kumar, Ghanashyam Madhukar Sonavane, Vishal Handa, Chandan Gupta +4 more | 2020-01-28 |
| 10528076 | Clock retiming circuit | Bhavin Odedara | 2020-01-07 |