Issued Patents 2020
Showing 1–3 of 3 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10719654 | Placement and timing aware wire tagging | Florian Braun, Lukas Dällenbach, Heinz Josef Hemmes, Jesse Peter Surprise, Marvin von der Ehe | 2020-07-21 |
| 10572618 | Enabling automatic staging for nets or net groups with VHDL attributes | Florian Braun, Lukas Dällenbach, Heinz Josef Hemmes, Marvin von der Ehe | 2020-02-25 |
| 10528323 | Circuit for addition of multiple binary numbers | Wilhelm Haller, Ulrich Krauch, Kurt Lind, Friedrich Schroeder | 2020-01-07 |