Issued Patents 2020
Showing 1–2 of 2 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10719654 | Placement and timing aware wire tagging | Manuel Beck, Florian Braun, Lukas Dällenbach, Jesse Peter Surprise, Marvin von der Ehe | 2020-07-21 |
| 10572618 | Enabling automatic staging for nets or net groups with VHDL attributes | Manuel Beck, Florian Braun, Lukas Dällenbach, Marvin von der Ehe | 2020-02-25 |