Issued Patents 2020
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10832763 | Global bit line latch performance and power optimization | Martin Bernhard Schmidt, Alexander Fritsch, Matthias Hock | 2020-11-10 |
| 10593420 | Testing content addressable memory and random access memory | Sheldon B. Levenstein, Pradip Patel, Daniel Rodko, Gordon B. Sapp, Rolf Sautter | 2020-03-17 |
| 10587248 | Digital logic circuit for deterring race violations at an array test control boundary using an inverted array clock signal feature | Werner Juchmes, Michael Kugel, Wolfgang Penth | 2020-03-10 |
| 10534884 | Layout of large block synthesis blocks in integrated circuits | Harald D. Folberth, Joachim Keinert, Sourav Saha | 2020-01-14 |