Issued Patents 2020
Showing 1–4 of 4 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10878152 | Single-bit latch optimization for integrated circuit (IC) design | Jose L. Neves, Alice H. Lee | 2020-12-29 |
| 10831938 | Parallel power down processing of integrated circuit design | Jose L. Neves | 2020-11-10 |
| 10831953 | Logic partition identifiers for integrated circuit design | Jose L. Neves | 2020-11-10 |
| 10831966 | Multi-fanout latch placement optimization for integrated circuit (IC) design | Jose L. Neves | 2020-11-10 |