Issued Patents 2020
Showing 1–14 of 14 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10855284 | Process of routing tile-to-tile interconnects of an FPGA, and method of manufacturing an FPGA | Yongning Liu, Fan Mo | 2020-12-01 |
| 10775433 | Programmable/configurable logic circuitry, control circuitry and method of dynamic context switching | Valentin Ossman, Anthony Kozaczuk | 2020-09-15 |
| 10693469 | Multiplier-accumulator circuit, logic tile architecture for multiply-accumulate, and IC including logic tile array | — | 2020-06-23 |
| 10684975 | One-hot-bit multiplexer control circuitry and technique | Fang YUAN | 2020-06-16 |
| 10686448 | Clock architecture, including clock mesh fabric for FPGA, and method of operating same | Nitish U. Natu, Abhijit M. Abhyankar | 2020-06-16 |
| 10686447 | Modular field programmable gate array, and method of configuring and operating same | Anthony Kozaczuk, Geoffrey R. Tate | 2020-06-16 |
| 10680616 | Block memory layout and architecture for programmable logic IC, and method of operating same | Geoffrey R. Tate | 2020-06-09 |
| 10679720 | Memory circuit and testing method thereof | — | 2020-06-09 |
| 10666262 | Programmable array logic | — | 2020-05-26 |
| 10666141 | Control device and power conversion circuit thereof with reconfigurable power structure | — | 2020-05-26 |
| 10587271 | Clock distribution and generation architecture for logic tiles of an integrated circuit and method of operating same | Nitish U. Natu | 2020-03-10 |
| 10587269 | Integrated circuit including an array of logic tiles, each logic tile including a configurable switch interconnect network | — | 2020-03-10 |
| 10566781 | Input/output buffer circuit with a protection circuit | Chai-Teck Gan | 2020-02-18 |
| 10551862 | System on chip with different current setting modes | — | 2020-02-04 |