Issued Patents 2020
Showing 1–2 of 2 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10665709 | Power semiconductor device integrated with ESD protection circuit under source pad, drain pad, and/or gate pad | Po-Chin Peng | 2020-05-26 |
| 10573736 | Heterojunction semiconductor device for reducing parasitic capacitance | Chun-Chieh Yang, Wen-Chia LIAO, Ching-Chuan Shiue, Shih-Peng Chen | 2020-02-25 |