Issued Patents 2020
Showing 1–3 of 3 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10860764 | Layer assignment technique to improve timing in integrated circuit design | Jhih-Rong Gao, Zhuo Li | 2020-12-08 |
| 10706201 | Circuit design routing using multi-panel track assignment | Mehmet Can Yildiz | 2020-07-07 |
| 10685164 | Circuit design routing based on parallel run length rules | Wing-Kai Chow, Gracieli Posser, Mehmet Can Yildiz, Zhuo Li | 2020-06-16 |