MO

Meir Ovadia

CS Cadence Design Systems: 6 patents #4 of 328Top 2%
Overall (2020): #23,971 of 565,922Top 5%
6
Patents 2020

Issued Patents 2020

Showing 1–6 of 6 patents

Patent #TitleCo-InventorsDate
10733345 Method and system for generating a validation test Matan Vax 2020-08-04
10698802 Method and system for generating a validation test 2020-06-30
10698805 Method and system for profiling performance of a system on chip 2020-06-30
10592703 Method and system for processing verification tests for testing a design under test 2020-03-17
10579761 Method and system for reconstructing a graph presentation of a previously executed verification test Talia Leah Orztizer 2020-03-03
10528691 Method and system for automated selection of a subset of plurality of validation tests 2020-01-07