| 10877894 |
Memory-side transaction context memory interface systems and methods, wherein first context and first address are communicated on plural wires during different clock cycles and second context (of block of the first context) is communicated on additional wire during one of the different clock cycles |
— |
2020-12-29 |
| 10877889 |
Processor-side transaction context memory interface systems and methods |
— |
2020-12-29 |
| 10862809 |
Modifying carrier packets based on information in tunneled packets |
— |
2020-12-08 |
| 10817412 |
Methods for migrating information stored in memory using an intermediate depth map |
J. Thomas Pawlowski, Robert M. Walker |
2020-10-27 |
| 10805392 |
Distributed gather/scatter operations across a network of memory nodes |
Amin Farmahini-Farahani |
2020-10-13 |
| 10713156 |
Systems and methods for memory system management |
Robert M. Walker |
2020-07-14 |
| 10684902 |
Method and apparatus for memory vulnerability prediction |
Vilas Sridharan |
2020-06-16 |
| 10672474 |
High-performance on-module caching architectures for non-volatile dual in-line memory module (NVDIMM) |
Amin Farmahini Farahani |
2020-06-02 |
| 10644004 |
Utilizing capacitors integrated with memory devices for charge detection to determine DRAM refresh |
Dmitri Yudanov |
2020-05-05 |
| 10599578 |
Dynamic cache bypassing |
Amin Farmahini Farahani |
2020-03-24 |
| 10592279 |
Multi-processor apparatus and method of detection and acceleration of lagging tasks |
Arkaprava Basu, Dmitri Yudanov, Mitesh R. Meswani, Sergey Blagodurov |
2020-03-17 |
| 10540200 |
High performance context switching for virtualized FPGA accelerators |
Kevin Y. Cheng, William C. Brantley |
2020-01-21 |
