Issued Patents 2020
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10810341 | Method and system for making pin-to-pin signal connections | Davis Boyd MOORE | 2020-10-20 |
| 10747929 | Resolving timing violations in multi-die circuit designs | Henri Fraisse, Dinesh D. Gaitonde | 2020-08-18 |
| 10715149 | Configurable logic block (CLB) internal routing architecture for enhanced local routing and clocking improvements | Eric F. Dellinger, Jay T. Young, Brian C. Gaide, Davis Boyd MOORE, Steven P. Young | 2020-07-14 |