Issued Patents 2019
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10460821 | Area efficient parallel test data path for embedded memories | Nikita Naresh, Vaskar Sarkar, Rajat Mehrotra | 2019-10-29 |
| 10331826 | False path timing exception handler circuit | Wilson Pradeep, Saket Jalan | 2019-06-25 |
| 10274538 | Full pad coverage boundary scan | Rajesh Mittal, Rajat Mehrotra | 2019-04-30 |
| 10184980 | Multiple input signature register analysis for digital circuitry | Naman Maheshwari, Wilson Pradeep | 2019-01-22 |