Issued Patents 2019
Showing 1–2 of 2 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10439620 | Dual-PFD feedback delay generation circuit | Theertham Srinivas, Jagdish Chand Goyal | 2019-10-08 |
| 10243573 | Phase syncronizing PLL output across reference and VCO clock domains | Jagdish Chand Goyal, Shankaranarayana Karantha, Ashwin Ravisankar, Srikanth Manian, Srinivas Theertham | 2019-03-26 |