Issued Patents 2019
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10515817 | Method for forming features of semiconductor structure having reduced end-to-end spacing | Xi-Zong Chen, Yun-Yu Hsieh, Cha-Hsin Chao | 2019-12-24 |
| 10510598 | Self-aligned spacers and method forming same | Yi-Tsang Hsieh, Cha-Hsin Chao, Yi-Wei Chiu, Ying Ting Hsia | 2019-12-17 |
| 10510596 | Metal gates of transistors having reduced resistivity | Chia-Ching Tsai, Yi-Wei Chiu | 2019-12-17 |
| 10495970 | Critical dimension uniformity | Xi-Zong Chen, Cha-Hsin Chao, Yi-Wei Chiu, Chih-Hsuan Lin | 2019-12-03 |
| 10460995 | Method of manufacture of a FinFET device | Chia-Ching Tsai, Yi-Wei Chiu | 2019-10-29 |
| 10304729 | Method of forming interconnect structures | Chia-Ching Tsai, Yi-Wei Chiu | 2019-05-28 |
| 10290547 | Method of manufacturing a semiconductor device with metal gate etch selectivity control | Chia-Ching Tsai, Yi-Wei Chiu | 2019-05-14 |
| 10269624 | Contact plugs and methods of forming same | Xi-Zong Chen, Y. H. Kuo, Cha-Hsin Chao, Yi-Wei Chiu | 2019-04-23 |
| 10269917 | Method of forming a FinFET with work function tuning layers having stair-step increment sidewalls | Yi-Chun Chen, Tsung Fan Yin, Ying Ting Hsia, Yi-Wei Chiu | 2019-04-23 |