| 10516725 |
Characterizing target material properties based on properties of similar materials |
Stephen Lee Smith, Yong-Seog Oh, Jie Liu, Michael C. Shaughnessy-Culver, Terry Sylvan Kam-Chiu Ma |
2019-12-24 |
| 10504988 |
2D material super capacitors |
Jamil Kawa |
2019-12-10 |
| 10489212 |
Adaptive parallelization for multi-scale simulation |
Stephen Lee Smith, Michael C. Shaughnessy-Culver, Jie Liu, Yong-Seog Oh, Pratheep Balasingam +1 more |
2019-11-26 |
| 10483171 |
Method and apparatus with channel stop doped devices |
— |
2019-11-19 |
| 10482212 |
Automated resistance and capacitance extraction and netlist generation of logic cells |
Zudian Qin, Karim El Sayed, Xi-Wei Lin |
2019-11-19 |
| 10417373 |
Estimation of effective channel length for FinFETs and nano-wires |
Yong-Seog Oh, Stephen Lee Smith, Michael C. Shaughnessy-Culver, Jie Liu |
2019-09-17 |
| 10411135 |
Substrates and transistors with 2D material channels on 3D geometries |
Joanne Huang, Jamil Kawa |
2019-09-10 |
| 10402520 |
First principles design automation tool |
Yong-Seog Oh, Michael C. Shaughnessy-Culver, Stephen Lee Smith, Jie Liu, Pratheep Balasingam +1 more |
2019-09-03 |
| 10388397 |
Logic timing and reliability repair for nanowire circuits |
Jamil Kawa |
2019-08-20 |
| 10381100 |
Enhancing memory yield and performance through utilizing nanowire self-heating |
Jamil Kawa |
2019-08-13 |
| 10312229 |
Memory cells including vertical nanowire transistors |
Jamil Kawa, Thu Nguyen |
2019-06-04 |
| 10311200 |
Pre-silicon design rule evaluation |
Karim El Sayed, Terry Sylvan Kam-Chiu Ma, Xi-Wei Lin, Qiang Lu |
2019-06-04 |
| 10256223 |
Cells having transistors and interconnects including nanowires or 2D material strips |
Jamil Kawa |
2019-04-09 |
| 10256293 |
Integrated circuit devices having features with reduced edge curvature and methods for manufacturing the same |
Lars Bomholt |
2019-04-09 |