ML

Min Li

SY Synopsys: 1 patents #61 of 330Top 20%
📍 Fremont, CA: #774 of 1,894 inventorsTop 45%
🗺 California: #27,528 of 67,890 inventorsTop 45%
Overall (2019): #341,930 of 560,194Top 65%
1
Patents 2019

Issued Patents 2019

Showing 1–1 of 1 patents

Patent #TitleCo-InventorsDate
10423742 Method to perform full accuracy hierarchical block level timing analysis with parameterized chip level contexts Qiuyang Wu, Martin Ranke 2019-09-24