Issued Patents 2019
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10372858 | Design-for-testability (DFT) insertion at register-transfer-level (RTL) | Eyal Odiz, Mukund Sivaraman | 2019-08-06 |
| 10354032 | Optimizing an integrated circuit (IC) design comprising at least one wide-gate or wide-bus | Eyal Odiz, Jovanka Ciric Vujkovic, Van E. Morgan | 2019-07-16 |