Issued Patents 2019
Showing 1–2 of 2 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10372858 | Design-for-testability (DFT) insertion at register-transfer-level (RTL) | Janet L. Olson, Mukund Sivaraman | 2019-08-06 |
| 10354032 | Optimizing an integrated circuit (IC) design comprising at least one wide-gate or wide-bus | Jovanka Ciric Vujkovic, Van E. Morgan, Janet L. Olson | 2019-07-16 |